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Features
* Low Voltage and Standard Voltage Operation * * * * * * * * * * * * * *
- 2.7 (VCC = 2.7V to 5.5V) - 1.8 (VCC = 1.8V to 5.5V) Internally Organized 2048 x 8 (16K) Two-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility Write Protect Pin for Hardware Data Protection Cascadable Feature Allows for Extended Densities 16-Byte Page Write Mode Partial Page Writes Are Allowed Self-Timed Write Cycle (10 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available 8-lead PDIP and 8-lead JEDEC SOIC Packages Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Two-Wire Serial EEPROM
16K (2048 x 8)
AT24C164(1)
Note: 1. Not recommended for a new design; Please refer to AT24C16B datasheet. For cascadability features of the AT24C164 (A0-A2), please move to the AT24C32C device which allows up to eight devices that may be addressed on a single bus system.
Description
The AT24C164 provides 16,384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 2048 words of 8 bits each. The device's cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C164 is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a twowire serial interface. In addition, this device is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Table 1. Pin Configurations
Pin Name A0 - A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect 8-lead PDIP 8-lead SOIC
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
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1
Absolute Maximum Ratings*
Operating Temperature..................................-55C to +125C Storage Temperature .....................................-65C to +150C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
WP
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Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that may be hardwired or actively driven to VDD or VSS. These inputs allow the selection for one of eight possible devices sharing a common bus. The AT24C164 can be made compatible with the AT24C16 by tying A2, A1 and A0 to VSS. Device addressing is discussed in detail in the device addressing section. WRITE PROTECT (WP): The write protect input, when tied low to GND, allows normal write operations. When WP is tied to VCC, all write operations are inhibited.
Memory Organization
The AT24C164 is internally organized with 256 pages of 8 bytes each. Random word addressing requires an 11 bit data word address.
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Table 2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V.
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Table 3. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 VCC3 VCC4 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL(1) VIH(1) VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Standby Current VCC = 5.0V Standby Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level Input High Level Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 Test Condition Min 1.8 2.5 2.7 4.5 0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05 Typ Max 5.5 5.5 5.5 5.5 1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Units V V V V mA mA A A A A A A V V V V
1. VIL min and VIH max are reference only and are not tested.
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Table 4. AC Characteristics Applicable over recommended operating range from TA = -40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time
(1)
5.0-volt Min Max 400 1.2 0.6 Units kHz s s 50 0.1 1.2 0.6 0.6 0 100 0.9 ns s s s s s ns 0.3 300 0.6 50 s ns s ns 10 1M ms Write cycles
Min
Max 100
4.7 4.0 100 0.1 4.7 4.0 4.7 0 200 1.0 300 4.7 100 10 1M 4.5
Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time
(1)
Inputs Fall Time(1) Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode
1. These parameters are characterized and is not 100% tested.
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Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C164 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, the AT24C164 can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
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Figure 2. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT WORDn
ACK
twr STOP CONDITION
Note:
(1)
START CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
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Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
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Device Addressing
The AT24C164 requires an 8-bit device address word following a start condition to enable the chip for read or write operations (see Figure 7 on page 10). The most significant bit must be a one followed by the A2, A1 and A0 device select bits (the A1 bit must be the compliment of the A1 input pin signal). The next 3 bits are used for memory block addressing and select one of the eight 256 x 8 memory blocks. These bits should be considered the three most significant bits of the data word address. The eighth bit of the device address is the read/write select bit. A read operation is selected if this bit is high or a write operation is selected if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11). PAGE WRITE: The AT24C164 is capable of a 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11). The data word address lower 4 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
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Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 10 on page 11). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 11 on page 11). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12). Figure 7. Device Address
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Figure 8. Byte Write
Figure 9. Page Write
Figure 10. Current Address Read
Figure 11. Random Read
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Figure 12. Sequential Read
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Ordering Information(1)
Ordering Code AT24C164-10PU-2.7(2) AT24C164-10PU-1.8(2) AT24C164-10SU-2.7(2) AT24C164-10SU-1.8(2) AT24C164-W2.7-11(3) AT24C164-W1.8-11(3) Notes: Package 8P3 8P3 8S1 8S1 Die Sale Die Sale Operation Range Lead-free/Halogen-free Industrial Temperature (-40C to 85C) Industrial Temperature (-40C to 85C)
1. Not recommended for new design; Please refer to AT24C16B datasheet. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables. 2. "U" designates Green package + RoHS compliant. 3. Available in waffle pack and wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options -2.7 -1.8 Low-Voltage (2.7V to 5.5V) Low-Voltage (1.8V to 5.5V)
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Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN - NOM - MAX NOTE
A A2 b b2 b3 c D
0.210 0.195 0.022 0.070 0.045 0.014 0.400
-
2
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240
0.130 0.018 0.060 0.039 0.010 0.365
-
5 6 6
3 3 4 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.310 0.250 0.100 BSC 0.300 BSC
0.325 0.280
Side View
4 0.150 2
0.115
0.130
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 b C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
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Revision History
Doc. Rev. 0105J
Comments Added note to 1st page; `Not recommended for new design; please refer to AT24C16B datasheet. For cascadability features of the AT24C164 (A0-A2), please move to the AT24C32C device which allows up to eight devices that may be addressed on a single bus system.'
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0105J-SEEPR-12/06

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